a adp3309 rev. b information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 www.analog.com fax: 781/326-8703 ?2004 analog devices, inc. all rights reserved. anycap 100 ma low dropout linear regulator functional block diagram thermal protection driver g m cc in adp3309 out r1 r2 gnd q1 err /nc sd band gap ref q2 features 1. 2% accuracy over line and load regulations @ 25 c ultralow dropout voltage: 120 mv typical @ 100 ma requires only c o = 0.47 f for stability anycap = stable with all types of capacitors (including mlcc) current and thermal limiting low noise low shutdown current: 1 a 2.8 v to 12 v supply range ?0 c to +85 c ambient temperature range several fixed voltage options ultrasmall sot-23-5 package excellent line and load regulations applications cellular telephones notebook, palmtop computers battery-powered systems pcmcia regulator bar code scanners camcorders, cameras general description the adp3309 is a member of the adp330x family of precision low dropout anycap voltage regulators. it is pin-for-pin and functionally compatible with national? lp2981, but offers performance advantages. the adp3309 stands out from con- ventional ldos with a novel architecture and an enhanced process. its patented design requires only a 0.47 f output capacitor for stability. this device is stable with any type of capacitor regardless of its esr (equivalent series resistance) value, including ceramic types for space restricted applications. the adp3309 achieves 1.2% accuracy at room temperature and 2.2% overall accuracy over temperature, line, and load regul ations. the dropout voltage of the adp3309 is only 120 mv (typical) at 100 ma. this device also includes a current limit and a shutdown feature. in shutdown mode, the ground current is reduced to ~1 a. the adp3309 operates with a wide input voltage range from 2.8 v to 12 v and delivers a load current in excess of 100 ma. the adp3309 anycap ldo offers a wide range of output voltages. for a 50 ma version, refer to the adp3308 data sheet. v out = 3.3v v in + adp3309-3.3 out err /nc on off sd gnd in c2 0.47 f c1 0.47 f + figure 1. typical application circuit
e2e rev. b adp3309especifications parameter symbol conditions min typ max unit output voltage accuracy v out v in = v outnom + 0.3 v to 12 v i l = 0.1 ma to 100 ma t a = 25 c e1.2 +1.2 % v in = v outnom + 0.3 v to 12 v i l = 0.1 ma to 100 ma e2.2 +2.2 % line regulation v in = v outnom + 0.3 v to 12 v t a = 25 c 0.02 mv/v load regulation i l = 0.1 ma to 100 ma t a = 25 c 0.06 mv/ma ground current i gnd i l = 100 ma 0.8 2.0 ma i l = 0.1 ma 0.19 0.3 ma ground current in dropout i gnd v in = 2.4 v i l = 0.1 ma 0.9 1.7 ma dropout voltage v drop v out = 98% of v outnom i l = 100 ma 0.12 0.25 v i l = 10 ma 0.025 0.07 v i l = 1 ma 0.004 0.015 v shutdown threshold v thsd on 2.0 v off 0.3 v shutdown pin input current i sdin 0 < v sd sd rdrresd sd de sd rresd sd de errree e e errr e e s edrre d se se es s
adp3309 e3e rev. b absolute maximum ratings * input supply voltage . . . . . . . . . . . . . . . . . . . e0.3 v to +16 v shutdown input voltage . . . . . . . . . . . . . . . . e0.3 v to +16 v power dissipation . . . . . . . . . . . . . . . . . . . . internally limited operating ambient temperature range . . . e55 c to +125 c operating junction temperature range . . . e55 c to +125 c ja . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 c/w jc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 c/w storage temperature range . . . . . . . . . . . . e65 c to +150 c lead temperature range (soldering 10 sec) . . . . . . . . . 300 c vapor phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . . 215 c infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 c * stresses above those listed under absolute maximum ratings may cause perma- nent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specitcation is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. only one absolute maximum rating may be applied at any one time. pin function descriptions pin name function 1i nr egulator input. 2g nd ground pin. 3 sd s err r r d e s sd d err e esde desd esd r esdsesedee d s es s ss rderde r d drree s r de drree s r de drree s r d drree s r d drree s r d drree s r d drree s r d drree s r d drree s r d drree s r d drree s r dr drree s r dr drree s r d drree s r d
adp3309 e4e rev. b etypical performance characteristics input voltage (v) output voltage (v) 3.302 3.298 3.295 3.3 4 14 56 789101 11213 3.301 3.300 3.297 3.296 3.299 v out = 3.3v i l = 0ma i l = 10ma i l = 100ma i l = 50ma tpc 1. line regulation: output voltage vs. supply voltage output load (ma) ground current ( a) 900 750 150 025 100 50 75 600 450 300 i l = 0 to 100ma tpc 4. quiescent current vs. load current output load (ma) input-output voltage (mv) 120 96 0 025 100 50 75 72 48 24 tpc 7. dropout voltage vs. output current output load (ma) output voltage (v) 3.302 3.295 010 100 20 30 40 50 60 70 80 90 3.301 3.300 3.299 3.298 3.297 3.296 v out = 3.3v v in = 7v tpc 2. output voltage vs. load current 0.2 e0.4 e45 e25 135 e5 15 35 75 95 115 55 0.1 0.0 e0.1 e0.2 e0.3 i l = 50ma i l = 100ma temperature ( c) output voltage (%) i l = 0ma tpc 5. output voltage variation % vs. temperature 5 4 0 01 0 234321 3 2 1 v out = 3.3v r l = 33 input/output voltage (v) input voltage (v) tpc 8. power-up/power-down input voltage (v) ground current ( a) 1150 900 0 0 1.2 12.0 2.4 3.6 4.8 6.0 7.2 8.4 9.6 10.8 650 400 150 v out = 3.3v i l = 0ma tpc 3. quiescent current vs. supply vo ltage temperature ( c) ground current ( a) 1250 1000 0 e25 e5 135 15 35 55 75 95 115 750 500 250 i l = 0ma v in = 7v i l = 100ma tpc 6. quiescent current vs. temperature time ( s) input/output voltage (v) 8.0 5.0 0 020 200 40 60 80 100 120 140 160 180 7.0 6.0 3.0 1.0 4.0 2.0 v sd = v in c l = 0.47 f r l = 33 v out = 3.3v v in v out tpc 9. power-up overshoot
adp3309 e5e rev. b volt s 3.320 3.290 040 400 80 120 160 200 240 280 320 360 3.310 3.300 7.0 3.280 7.5 v out = 3.3v r l = 33 c l = 0.47 f v in time ( s) tpc 10. line transient response 3.320 3.310 0 100 500 200 300 400 3.290 3.280 100 10 3.300 volt s ma time ( s) v out = 3.3v c l = 4.7 f i out tpc 13. load transient volts 4 3 010 50 20 30 40 1 0 3 0 2 time ( s) v sd v out = 3.3v r l = 33 c l = 0.47 f 3.3v tpc 16. turn off time ( s) volts 3.320 3.290 020 200 40 60 80 100 120 140 160 180 3.310 3.300 7.0 3.280 7.5 v out = 3.3v r l = 3.3k c l = 0.47 f v in tpc 11. line transient response v out = 3.3v ma 300 200 01 5 234 0 4 2 0 100 volt s v out i out time (sec) 0.5 4.5 1.5 2.5 3.5 tpc 14. short circuit current frequency (hz) ripple rejection (db) 10 100 10m 1k 10k 1m 0 e10 e100 e20 e30 e40 e50 e60 e70 100k a. 0.47 f, r l = 33k b. 0.47 f, r l = 33 c. 10 f, r l = 33k d. 10 f, r l = 33 v out = 3.3v d c b a e80 e90 d b c a tpc 17. power supply ripple rejection 3.320 3.310 0 100 500 200 300 400 3.290 3.280 100 10 3.300 volts ma time ( s) v out = 3.3v c l = 0.47 f i out tpc 12. load transient volt s 4 3 0 020 100 40 60 80 2 1 0 3 v sd c l = 0.47 f v out 3.3v c l = 4.7 f v out = 3.3v r l = 33 3v time ( s) tpc 15. turn on 10 1 0.01 100 1k 100k 10k 0.1 frequency (hz) voltage noise spectral density ( v hz) v out = 3.3v, c l = 0.47 f i l = 1ma tpc 18. output noise density
adp3309 e6e rev. b theory of operation the adp3309 anycap ldo uses a single control loop for regulation and reference functions. the output voltage is sensed by a resistive voltage divider consisting of r1 and r2, which is varied to provide the available output voltage option. feedback is taken from this network by way of a series diode (d1) and a second resistor divider (r3 and r4) to the input of an amplifier. g m ptat v os noninverting wideband driver input q1 adp3309 compensation capacitor attenuation (v band gap /v out ) r1 d1 r2 output ptat current r load c load (a) gnd r4 r3 figure 2. functional block diagram a very high gain error amplifier is used to control this loop. the amplifier is constructed in such a way that at equilibrium it produces a large, temperature proportional input offset volt- age that is repeatable and very well controlled. the tempera ture proportional offset voltage is combined with the com ple- mentary diode voltage to form a virtual band gap voltage, im- plicit in the network, although it never appears explicitly in the circuit. ultimately, this patented design makes it possible to control the loop with only one amplifier. this technique also improves the noise characteristics of the amplifier by providing more flexibility on the trade-off of noise sources that leads to a low noise design. the r1, r2 divider is chosen in the same ratio as the band gap voltage to the output voltage. although the r1, r2 resistor divider is loaded by the diode d1, and a second divider consist- ing of r3 and r4, the values can be chosen to produce a tem- perature stable output. the patented amplifier controls a new and unique noninverting driver that drives the pass transistor, q1. the use of this special noninverting driver enables the frequency compensation to include the load capacitor in a pole splitting arrangement to achieve reduced sensitivity to the value, type, and esr of the load capacitance. most ldos place very strict requirements on the range of esr values for the output capacitor because they are difficult to stabilize due to the uncertainty of load capacitance and resistance. moreover, the esr value, required to keep con- ventional ldos stable, changes depending on load and temperature. these esr limitations make designing with ldos more difficult because of their unclear specifications and extreme variations over temperature. this is no longer true with the adp3309 anycap ldo. it can be used with virtually any capacitor, with no constraint on the minimum esr. this innovative design allows the circuit to be stable with just a small 0.47 f capacitor on the output. addi- tional advantages of the design scheme include superior line noise rejection and very high regulator gain which leads to excel- lent line and load regulation. an impressive 2.2% accuracy is guaranteed over line, load, and temperature. additional features of the circuit include current limit and ther- mal shutdown. compared to the standard solutions that give warning after the output has lost regulation, the adp3309 pro- vides improved system performance by enabling the err err r s d esr d esresr s d d p d = ( v in e v out ) i load + ( v in ) i gnd where i load and i gnd are load current and ground current, v in and v out are input and output voltages, respectively. assuming i load = 100 ma, i gnd = 2 ma, v in = 5.0 v, and v out = 3.3 v, device power dissipation is p d = (5.0 e 3.3) 100 ma + 5.0 2 ma = 180 mw t = t j e t a = p d j a = 0.18 190 = 34.2 c
adp3309 e7e rev. b with a maximum junction temperature of 125 c, this yields a maximum ambient temperature of ~90 c. printed circuit board layout consideration surface-mount components rely on the conductive traces or pads to transfer heat away from the device. appropriate pc board layout techniques should be used to remove heat from the immediate vicinity of the package. the following general guidelines will be helpful when designing a board layout: 1. pc board traces with larger cross section areas will remove more heat. for optimum results, use pc boards with thicker copper and/or wider traces. 2. increase the surface area exposed to open air so heat can be removed by convection or forced air flow. 3. do not use solder mask or silk screen on the heat dissipating traces because it will increase the junction to ambient thermal resistance of the package. shutdown mode a pplying a ttl high signal to the shutdown pin or tying it to the input pin will turn the output on. pulling the shutdown pin d own to a ttl low signal or tying it to ground will turn the output off. in shutdown mode, quiescent current is reduced to less than 1 a. error flag dropout detector t he adp3309 will maintain its output voltage over a wide range of load, input voltage, and temperature conditions. if the output is about to lose regulation, for example, by reducing the supply voltage below the combined regulated output and drop- out voltages, the err err err rs s d see d sd d d sd d s d d sd d e desssed err r r dr d d d s s d dd r r d d sd r r dr
adp3309 e8e rev. b c00141e0e7/04(b) 5-lead small outline transistor package [sot-23] (rt-5) dimensions shown in millimeters pin 1 1.60 bsc 2.80 bsc 1.90 bsc 0.95 bsc 1 3 4 5 2 0.22 0.08 10 5 0 0.50 0.30 0.15 max seating plane 1.45 max 1.30 1.15 0.90 2.90 bsc 0.60 0.45 0.30 compliant to jedec standards mo-178aa outline dimensions revision history location page 7/04?data sheet changed from rev. a to rev. b. changes to ordering guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 updated outline dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
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